Jitter peaking what is

We demonstrate that the ring oscillator phase … Expand. View 5 excerpts, cites methods and results. View 13 excerpts, cites methods and background. View 1 excerpt, cites methods. In this paper, delay-locked loop's DLLs jitter due to uncertainties in the phase frequency detector PFD is calculated.

First, time-domain equations of the DLL are introduced. These equations are … Expand. View 2 excerpts, cites background. Jitter issues in clock conditioning with FPGAs.

View 11 excerpts, cites background and methods. A MHz clock recovery delay- and phase-locked loop. The authors describe a completely monolithic delay-locked loop DLL which may be used either by itself as a deskewing element or in conjunction with an external voltage-controlled crystal oscillator … Expand. View 2 excerpts, references background. The phase locked loop signal recovery apparatus further includes an integrating amplifier, receiving as input the output signal of the phase detector and generating as output a control signal proportional to a time integral of the output signal of the phase detector, a variable frequency oscillator, receiving as input the control signal and providing as an output a signal whose frequency varies in response to the control signal, and a variable phase shifter, receiving as input an undelayed signal and the control signal, and providing as output a delayed signal that differs in phase from the undelayed signal by a phase shift that varies in response to the control signal.

The phase locked loop signal recovery apparatus is characterized in that the incoming data stream provides the undelayed signal of the variable phase shifter, the output of the variable phase shifter couples to the first input of the phase detector, and said output of the variable frequency oscillator couples to the second input of the phase detector.

According to a second aspect of the invention, a phase-locked-loop-implemented method is provided for recovering a periodic signal from an incoming signal to produce a regenerated signal, without amplifying phase jitter in the incoming signal. The phase locked loop performs the steps of comparing a phase of a first signal, derived from the incoming signal, with a phase of a second signal, derived from the regenerated signal, to produce a phase difference signal that is proportional, by a gain, G1, to a difference between the phase of the first and second signals.

The phase locked loop further performs the steps of integrating the phase difference signal with respect to time to produce an integrated phase difference signal that is proportional, by a gain G2, to the phase difference signal, converting the integrated phase difference signal into a frequency to produce a frequency output signal that is proportional, by a gain, G3, to a magnitude of the integrated phase difference signal, and delaying one of the incoming signal and the regenerated signal an amount of time proportional, by a gain, G4, to the magnitude of the integrated phase difference signal to produce a delayed signal.

The phase-locked-loop-implemented method is characterized in that the step of delaying includes delaying the incoming signal to generate the first signal. The invention will now be described by way of example only with reference to the following figures in which:. A typical phase-locked loop suitable for clock recovery purposes is shown in Fig. Incoming data on line enters a phase detector Phase detector receives another input on line which input is a clock signal developed by voltage-controlled oscillator VCO on line Phase detector compares the phase of the clock signal on line to that of the data on line and develops a phase error signal on line which error signal is indicative of the difference in phase between the clock signal and the incoming data.

The phase error signal on line is provided to a loop amplifier and filter which develops a control voltage that is used to adjust the output of VCO so that the phase error detected by phase detector is reduced to zero. The incoming data on line can then be re-timed by conventional circuitry not shown. Corresponding elements in Figs. For example, VCO in Fig.

In accordance with conventional network theory, phase detector is represented by a summer As previously mentioned, in order to insure that the phase error is driven to zero, loop amplifier and filter includes an integrator plus other conventional circuitry so that the transfer function of the amplifier and filter circuit contains an explicit zero necessary for loop stability.

A straightforward feedback analysis of the linearized circuit shown in Fig. It is possible to show that the jitter transfer function in expression 1 exceeds unity in at least one frequency band as shown in frequency band in the plot of the jitter transfer function vs log frequency in Fig.

This phenomenon is the cause of "jitter peaking" as mentioned above. For phase-locked loops that are cascaded, the "jitter peaking" is multiplicitive and, thus, becomes a serious problem. It includes a phase detector , loop amplifier and filter and VCO Equivalent parts in the loop shown in Fig. The conventional phase-locked loop architecture has been modified, however, by the addition of a voltage-controlled phase-shifter in series with the incoming data stream.

Incoming data on line is provided to phase-shifter which develops a delayed data stream wherein the delay is proportional to a control voltage provided on line The delayed data is then provided as the input data to phase-locked loop The control voltage on line is developed by the loop amplifier and filter and is the same voltage applied to VCO via line As in the phase-locked loop shown in Fig.

However, an explicit transfer function zero in the loop amplifier and filter is no longer necessary because phase shifter stabilizes the loop. More particularly, a linearized block diagram for the phase-locked loop system of Fig. The voltage-controlled phase shifter is represented by a gain block in series with a summer It should also be noticed that the loop amplifier and filter is represented by simple integrator which does not include an explicit zero.

From the diagram in Fig. Using a first or second order of low-pass filter as the loop filter reduces the high frequency jitter amplification. Meanwhile, low frequency jitter amplification could be decreased using a suitable band-pass filter after the delay line.

Care should be taken to consider the accuracy and limitations of the oscilliscope or other measurement equipment when measuring any clock source. Accumulated jitter is larger than the period jitter, as it the the accumulation of the period jitter over many cycles. In real systems, we only need to consider the jitter over specific bandwidths, so the accumulated jitter will reach a limit independent of time and will not become infinitely large.

Accumulated jitter is the sum of both random and deterministic components. Accumulated jitter is integrated over a frequency band that matches the application.

For example, in an RF system, the integration band may match the bandwidth of the channel used to carry the data. In a SerDes the integration band generally matches the region outside the bandwidth of the clock and data recovery CDR used to sample the received data. Figure 5 and Figure 6 show the three ways that Jitter is usually quantified:. RMS, peak and peak-to-peak can all be used to quantify any of the three types of jitter discussed in section 4: period jitter, cycle-to-cycle jitter and accumulated jitter.

Peak-to-peak jitter is twice the peak jitter, because in almost all cases the probability distribution is symmetric. In principle it is possible to have an asymmetric distribution, but this is so rare that it can be neglected.

Conversion between RMS jitter and peak jitter is more complicated because a normal distribution is unbounded, so in principle there is an infinitesimally small but non-zero chance of infinite instantaneous jitter on any sample.

However, this is a theoretical limit and in practice, the bandwidth limited nature of PLLs and other clock sources mean that jitter tails will be truncated.

In particular, because period jitter is measured across a single period, the bandwidth within which the period can be modified is very limited, so the real probability will be lower than calculated. The designer of a system must choose the acceptable probability of jitter being above the peak jitter, i.

From this, the ratio between peak and sigma can be determined. The table below, gives the probabilities that a peak value will be exceeded for different multiples of the RMS value. Commonly used multiple within SerDes specifications for accumulated jitter. Often specified as a bit error rate BER of 2. Julian has several US and international patents as a result of this work. He has participated in an impressive list of high-speed analog and mixed-signal ICs that are in commercial production.

Feel free to contact Julian if you have questions about this topic. If you wish to download a copy of this white paper, click here. No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.

Design And Reuse. Applications Different applications have different requirements for jitter. Digital Systems In a digital system, the clock defines a period of time during which the circuits can achieve a certain amount of work. This is related to the frequency by the following equation: In digital systems, clock edges define the time at which each work unit starts and ends. RF Systems The Local Oscillator LO for an RF system defines the carrier frequency and is generally used in the mixers used to generate the transmitted signal and down-convert the received signal for processing.

Serial Communications When transmitting or receiving a serial bit stream, using a SerDes or similar, the clock is used to encode and time the transmitted data, embedding clock information within the transmitted data itself. Random and Deterministic Jitter When measuring jitter, it is important to consider the behaviour across many cycles to see what the aggregate performance will be in a statistical sense.

Figure 1: The Normal Distribution Figure 1 shows the normal distribution, typically used to model jitter probability. Deterministic Jitter DJ Deterministic jitter is jitter that follows a known pattern. Potential sources of deterministic jitter in clock outputs are: Spread spectrum clocking SSC Deterministic modulation of the power supply e.

Other sources of modulation Any other mechanism that operates in a deterministic manner In data transmission systems, data dependent jitter DDJ is a deterministic jitter component that depends on the prior data symbols that have been transmitted. Deterministic jitter components, including DDJ, add linearly.

Combining Random and Deterministic Jitter Only the peak or peak-to-peak values of random and deterministic jitter can be combined. To combine these two components: Take the peak value of the random jitter for a given sigma R j Take the peak value of the deterministic jitter Add the two peak values to calculate total jitter T j.